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On November 20, 2018, the third-generation semiconductor industry technology innovation strategic alliance ("CASA") released three alliance standards T/CASA 003-2018 "4H-SiC epitaxial wafers for p-IGBT devices", T/CASA004. 1 "4H Silicon Carbide Substrate and Epitaxial Layer Defect Terminology", T/CASA004.2 "4H-SiC Substrate and Epitaxial Layer Defect Map". The three standards were led by Sun Guosheng, technical director of Dongguan Tianyu Semiconductor Technology Co., Ltd., and were repeatedly considered, revised, and compiled in accordance with the CASA standard formulation procedures (project establishment, draft for comments, committee draft, and release draft). The development of the standard is supported by many formal members of the CASA standardization committee.

The main drafting units of the standard include: Dongguan Tianyu Semiconductor Technology Co., Ltd., Global Energy Internet Research Institute Co., Ltd., China Electronics Technology Group Corporation 55th Research Institute, Zhuzhou CRRC Times Electric Co., Ltd., Shandong Tianyue Crystal Materials Co., Ltd. Company, Institute of Microelectronics, Chinese Academy of Sciences, Han Tiancheng Electronic Technology (Xiamen) Co., Ltd., Shandong University, Taizhou Yineng Technology Co., Ltd., China Electronics Technology Group Corporation Thirteenth Research Institute, Shenzhen Third Generation Semiconductor Research Institute.
 
T/CASA 003-2018 "4H-SiC epitaxial wafers for p-IGBT devices" specifies the classification and marking, requirements, test methods, inspection rules, marking, packaging, transportation and storage of 4H SiC epitaxial wafers. The appendix describes in detail the use of optical imaging to quickly obtain defects on the surface of 4H-SiC epitaxial wafer samples, the use of atomic force microscopy to obtain surface roughness, and the detection method of epitaxial layer thickness and doping concentration in detail.
 
T/CASA004.1-2018 "Terminology of 4H Silicon Carbide Substrate and Epitaxial Layer Defects" specifies the terms and definitions of 4H silicon carbide substrate and epitaxial layer defects, including 4H-SiC materials, common terms of defects, substrate defects, epitaxy Layer defects and process defects are divided into five parts, in which process defects include defects caused by related processes such as polishing (CMP), ion implantation, high temperature annealing and oxidation.
 
T/CASA004.2-2018 "4H-SiC substrate and epitaxial layer defect map" standard describes the map of 4H-SiC substrate and epitaxial defects, including 4H-SiC substrate defects, epitaxial defects and defects generated by the process; The main defects, process and processing defects of 4H silicon carbide (4H-SiC) substrate and epitaxial layer are given, and the characteristics and properties of defects and their influence on epitaxial growth or device characteristic parameters are explained. , analyzed the causes and elimination methods, and classified them.

Substrate defects include dislocations, stacking faults, micropipes, carbon inclusions, crystal inclusions, double Shockley stacking faults, screw dislocations, edge dislocations, base plane dislocations, small angle grain boundaries, scratches , CMP implied scratches;
Epitaxial defects include surface topography defects, falling particles, triangular defects, comet defects, carrot defects, linear defects, pit defects, trapezoidal defects, step defects, epitaxial bumps, papillae, interfacial dislocations, primary stacking faults , incomplete dislocation, half ring array, point defect, carbon vacancy, epitaxial layer screw dislocation, epitaxial layer edge dislocation, epitaxial layer base plane dislocation;
In terms of process defects, high-temperature annealing defects, oxidation defects, electrical stress-induced defects, electrical stress-induced triangular stacking faults, electrical stress-induced stripe stacking faults, and dry etching defects.
 
The CASA Standardization Committee will focus on the synergy mechanism of scientific and technological innovation, standard development and industrial development, and explore a new model of improving the level of technical standards through scientific research and development, and promoting the transformation and application of scientific and technological achievements through technical standards. Development, promote the technological progress and industrialization of third-generation semiconductors, and improve the overall competitiveness of my country's third-generation semiconductor industry.

The CASA Standardization Committee has released the "Report on the Standard System of the Third Generation Semiconductor Power Electronics Industry", "Report on the Test Conditions and Capabilities of the Third Generation Semiconductor Power Electronics Industry", and the Alliance Standard T/CASA001-2018 "General Technology of SiC Schottky Barrier Diodes" Specification", Alliance Technical Report T/CASA/TR 001-2018 "Technical Report on the Application of SiC Devices in DC/DC Charging Modules", T/CASA 003-2018 "4H-SiC Epitaxial Wafers for p-IGBT Devices", T/CASA004 .1-2018 "4H Silicon Carbide Substrate and Epitaxial Layer Defect Terminology", T/CASA004.2-2018 "4H-SiC Substrate and Epitaxial Layer Defect Map", etc. Alliance standards under development include T/CASA002-201X "Wide Bandgap Semiconductor Terminology Standard", T/CASA005-201X "General Technical Specification for GaN HEMT Power Electronic Devices", T/CASA006-201X "General Technical Specification for Silicon Carbide Metal-Oxide-Semiconductor Field Effect Transistor", T/CASA007 -201X "Evaluation of SiC MOS Modules for Electric Vehicles", etc.